Stereo Vision IP Suite

Stereo Vision for FPGA

Implementation for small lot production of many products (with low cost & low power)
Requirement using common platform with later process customization by applications

FUJISOFT Proposal

We chose an algorithm developed by Dr. Keiji Saneyoshi, and associate Professor of Tokyo Institute of Technology, who is a leading researcher on stereo camera technologies for vehicles.
Compared with MPU and DSP, high frame rate with low power consumption is realized.
⇒Enabling 1280x720/30fps, VGA/60fps with small logic size: 25.6K ALMs(67.7K LE)
Including object detection
Modular design, supporting Avalon-STI/F

Block Diagram

FUJISOFT Development segment responsibility

Distance measurement sensor hardware & software development implemented into Stereo camera

Responsibility	[Hardware] Object detection IP, Object tracking IP, FPGA design, Tests [software] Driver(s), Control application(s)
Key technologies	Electronic circuit RTL language, C language
Circuit design	FPGA
FPGA design	several controllers
Driver development	PC deriver(s)
Application development	Distance measurement sensor control application(s)

This product is selected in.

Cyclone^® V SoC FPGA

Intel

Intel

Company:: Intel Programmable Solution Group (former Altera)

Location:: San Jose CA. U.S

Establishment:: 1983

Business:: Programmable Logic Solutions

Products:: FPGA, SoC, CPLD development software, IPs

Web site:: https://www.altera.com/

FUJISOFT is a Altera Certified Development Partner.